Output drivers are typically used, in part, to ensure that the generated output voltages stay within predefined limits. FIG. 1 is a transistor schematic diagram of a CMOS output driver 10, as known in the prior art. Current flowing through current source 30 is mirrored in transistor 12 using transistor 28, and current flowing through current source 240 is mirrored in transistor 14 using transistor 24.
If input voltage Vin applied to the gate terminals of transistors 20 and 22 is greater than voltage Vip applied to the gate terminals of transistor 18 and 16, node Vop is pulled to a lower voltage relative to node Von. Conversely, if input voltage Vin is smaller than voltage Vip, node Vop is raised to a higher voltage relative to node Von.
In accordance with one known standard, resistive load Rload has a resistance of 100 ohms. At VDD supply voltage of 3.3 volts, with single-ended peak voltage of 400 mv across nodes VOP VON, and a common-mode voltage of 1.2 volts, a current of 4 mA is consumed thus resulting in the power consumption of 13.2 mW. As the supply voltage VDD goes down, to e.g. 1.8 volts, transistor 12 starts to enter the linear region of operation thus rendering output driver 100 inoperative. Accordingly, a need continues to exist for a CMOS output driver adapted to operate at relatively low voltages while maintaining the proper voltage across external loads.